----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    19:42:22 04/25/2012 
-- Design Name: 
-- Module Name:    Cyclone - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.definitions.all;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Cyclone is
    Port (
            clk_i : in STD_LOGIC;
            clr_i : in STD_LOGIC;
            instr_ack_i : in STD_LOGIC;
            instr_word_i : in STD_LOGIC_VECTOR (17 downto 0);
            data_ack_i : in STD_LOGIC;
            data_word_i : in STD_LOGIC_VECTOR (7 downto 0);
            port_ack_i : in STD_LOGIC;
            port_word_i : in STD_LOGIC_VECTOR (7 downto 0);
            int_req : in STD_LOGIC;
            int_ack : out STD_LOGIC;
            instr_cyc_o : out STD_LOGIC;
            instr_stb_o : out STD_LOGIC;
            instr_addr_o : out STD_LOGIC_VECTOR (9 downto 0);
            data_cyc_o : out  STD_LOGIC;
            data_stb_o : out  STD_LOGIC;
			   data_we_o : out STD_LOGIC; 
            data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
            data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
            port_cyc_o : out  STD_LOGIC;
            port_stb_o : out  STD_LOGIC;
            port_we_o : out  STD_LOGIC;
            port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
            port_word_o : out  STD_LOGIC_VECTOR (7 downto 0));
end Cyclone;

architecture Behavioral of Cyclone is

component ControlUnit is
 Port (    clr : in  STD_LOGIC;
           clk : in  STD_LOGIC;
			  inst_ack_in : in STD_LOGIC;
			  data_ack_in : in STD_LOGIC;
			  port_ack_in : in STD_LOGIC;
			  cu_mem_op : out STD_LOGIC;
			  is_branch: out STD_LOGIC;
			  is_reti: out STD_LOGIC;
			  is_sub_ret: out STD_LOGIC;
			  is_jump: out STD_LOGIC;
			  is_call: out STD_LOGIC;
			  is_immediate: out STD_LOGIC;
			  is_shift: out STD_LOGIC;
			  is_interrupt: out STD_LOGIC;
			  is_rw: out STD_LOGIC;
			  interrupt: in STD_LOGIC;
			  pc_reset: out STD_LOGIC;
			  loadEnable_IR: out STD_LOGIC;
			  enable_acc: out STD_LOGIC;
			  enable_data: out STD_LOGIC;
			  enable_flags: out STD_LOGIC;
			  ena_mem_port_data: out STD_LOGIC;
			  opType: out STD_LOGIC_VECTOR(2 downto 0);
			  branchOp: out STD_LOGIC_VECTOR (1 downto 0);
			  IR: in STD_LOGIC_VECTOR(17 downto 0);
           uc_status : out state_type );
end component;

component DataPath is
    Port ( 
	        clk : in  STD_LOGIC;
			  clr: in STD_LOGIC;
			  instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           reg_in : in  STD_LOGIC_VECTOR (7 downto 0);
           is_branch : in  STD_LOGIC;
			  branchOp : in STD_LOGIC_VECTOR (1 downto 0);
           is_reti : in  STD_LOGIC;
           is_sub_ret : in  STD_LOGIC;
           is_jump : in  STD_LOGIC;
           is_intr : in  STD_LOGIC;
			  is_call: in STD_LOGIC; -- IMPORTANTE PARA CAPTADOR Y ACTIVAR ESCRITURA EN STACK (STACK_OP=1 ENABLESTACK= 1)
           loadEnable_IR : in  STD_LOGIC;
           pc_reset : in  STD_LOGIC;
           is_interrupt : in  STD_LOGIC;
           enable_data : in  STD_LOGIC;
           is_rw : in  STD_LOGIC;
           is_shift : in  STD_LOGIC;
           opType : in  STD_LOGIC_VECTOR (2 downto 0);
           enable_acc : in  STD_LOGIC;
           enable_flags : in  STD_LOGIC;
           is_immediate : in  STD_LOGIC;
           mem_acc : in  STD_LOGIC;
		     is_end_interrupt: in  STD_LOGIC;
			  instr_addr_o : out STD_LOGIC_VECTOR (9 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
          -- port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
          -- port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           IR_o : out  STD_LOGIC_VECTOR (17 downto 0));
end component;


component IOInterface is
    Port ( instr_ack_i : in  STD_LOGIC;
           instr_word_i : in  STD_LOGIC_VECTOR (17 downto 0);
           data_ack_i : in  STD_LOGIC;
           data_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
           port_ack_i : in  STD_LOGIC;
           port_word_i : in  STD_LOGIC_VECTOR (7 downto 0);
			  cu_status : in state_type;
			  cu_mem_op : in STD_LOGIC;
			  ena_mem_port_data : in STD_LOGIC;
			  mem_rw : in STD_LOGIC;
			  datapath_word_o : in STD_LOGIC_VECTOR (7 downto 0);
			  datapath_addr_o : in STD_LOGIC_VECTOR (7 downto 0);
			  
			  pc: in  STD_LOGIC_VECTOR (9 downto 0);
			  		  
			  instr_reg : out STD_LOGIC_VECTOR (17 downto 0);
			  data_reg : out STD_LOGIC_VECTOR (7 downto 0);
           instr_cyc_o : out  STD_LOGIC;
           instr_stb_o : out  STD_LOGIC;
           instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
           data_cyc_o : out  STD_LOGIC;
           data_stb_o : out  STD_LOGIC;
			  data_we_o : out STD_LOGIC; 
           data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_cyc_o : out  STD_LOGIC;
           port_stb_o : out  STD_LOGIC;
           port_we_o : out  STD_LOGIC;
           port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
			  instr_ack_to_cu : out STD_LOGIC;
			  data_ack_to_cu : out STD_LOGIC;
			  port_ack_to_cu : out STD_LOGIC);
end component;

-- signals de unidad de control
signal     cu_mem_op , is_branch, is_reti, is_sub_ret, is_jump, is_call,  is_immediate, 
			  is_shift,is_interrupt, is_rw, pc_reset, loadEnable_IR, enable_acc, enable_data, enable_flags, ena_mem_port_data:  STD_LOGIC;
signal			  opType:  STD_LOGIC_VECTOR(2 downto 0);
signal			  branchOp:  STD_LOGIC_VECTOR (1 downto 0);
signal           uc_status :  state_type ;

-- signals out de datapath
signal 	  instr_addr_pc : STD_LOGIC_VECTOR (9 downto 0);
signal     IR_o :   STD_LOGIC_VECTOR (17 downto 0);
signal     data_word_o_s :   STD_LOGIC_VECTOR (7 downto 0);
signal     data_addr_o_s :   STD_LOGIC_VECTOR (7 downto 0);

-- signals out de E y s
signal   instr_reg :  STD_LOGIC_VECTOR (17 downto 0);
signal 	data_reg :  STD_LOGIC_VECTOR (7 downto 0);
signal   instr_ack_to_cu , data_ack_to_cu , port_ack_to_cu : STD_LOGIC;			  
          -- instr_cyc_o : out  STD_LOGIC;
          -- instr_stb_o : out  STD_LOGIC;
          -- instr_addr_o : out  STD_LOGIC_VECTOR (9 downto 0);
			---data_cyc_o : out  STD_LOGIC;
          -- data_stb_o : out  STD_LOGIC;
			 -- data_we_o : out STD_LOGIC; 
           --data_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
           --data_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
         --  port_cyc_o : out  STD_LOGIC;
          -- port_stb_o : out  STD_LOGIC;
          -- port_we_o : out  STD_LOGIC;
          -- port_addr_o : out  STD_LOGIC_VECTOR (7 downto 0);
          -- port_word_o : out  STD_LOGIC_VECTOR (7 downto 0);
			 


begin

--OP_PC: RegistroPC port map(clk, clr, pc_in, loadEnable_IR, pc_out);

DATA_PATH: Datapath port map  ( 
	        clk_i, clr_i, instr_word_i ,data_reg ,is_branch , branchOp,is_reti ,is_sub_ret ,
           is_jump ,is_interrupt , is_call , loadEnable_IR ,pc_reset ,is_interrupt ,
           enable_data ,is_rw ,  is_shift, opType , enable_acc, enable_flags,
           is_immediate , cu_mem_op , is_reti, instr_addr_pc,
           data_word_o_s,data_addr_o_s, IR_o );

CU: ControlUnit port map(    clr_i ,clk_i , instr_ack_to_cu, data_ack_to_cu,  port_ack_to_cu ,cu_mem_op ,
			  is_branch, is_reti, is_sub_ret,is_jump , is_call, is_immediate,
			  is_shift, is_interrupt, is_rw , int_req, pc_reset, loadEnable_IR, enable_acc,
			  enable_data, enable_flags, ena_mem_port_data, opType, branchOp, instr_reg,
           uc_status);

IO: IOInterface port map( instr_ack_i,instr_word_i, data_ack_i ,data_word_i, port_ack_i, port_word_i ,
			  uc_status , cu_mem_op , ena_mem_port_data , is_rw , data_word_o_s ,
			  data_addr_o_s ,instr_addr_pc ,
			  		  
			  instr_reg,data_reg , instr_cyc_o , instr_stb_o , instr_addr_o ,
           data_cyc_o , data_stb_o ,  data_we_o, data_addr_o ,data_word_o ,
           port_cyc_o , port_stb_o ,  port_we_o ,  port_addr_o , port_word_o ,
			  instr_ack_to_cu , data_ack_to_cu , port_ack_to_cu );


int_ack <= is_interrupt;

end Behavioral;

